The present invention relates broadly to semiconductor devices and integrated circuits, and in particular to the method and process for fabricating a dielectrically isolated junction field effect transistor and PNP transistor.
The integrated circuit art has developed to the point where a plurality of transistors, diodes, field effect devices, capacitors, and resistors may be provided with a unitary body of semiconductive material. At this stage in the art integrated circuit fabrication is keyed to the fabrication of bipolar transistor structures, that is, the individual operations performed and tailored to provide a bipolar transistor structure of desired characteristics in the integrated circuit are preferably, and almost necessarily as an economic matter, used for the simultaneous fabrication of the other types of elements in the integrated circuit so as to minimize fabrication time, expense and the extent and number of times to which the structure is required to be heated and handled and to minimize the number of individual process steps that require close control so as to realize a satisfactory overall yield. It is naturally also the case that integrated structures should compete favorably as to engineering performance with single component circuits.
However, as semiconductor devices and integrated circuits become more sophisticated and are required to provide more complex functions, precise junction control becomes a critical process requirement. It is well understood that tight resistivity control and exact thickness with sharp nongraded junction control of the various regions comprising the semiconductor device become more crucial as the complexity increases. Generally, the more complex the function which the device is to provide, the more exact the process parameters must be, with smaller tolerances allowed for an operative device. To make such precisely characterized devices reproducible in large scale production, a manufacturing process is required which minimizes the process variables.